UPIO-M3U1XX Datasheet, PDF (24/28 Pages) Silicon Laboratories – The Unified Development Platform (UDP) provides a development

UPIO-M3U1xx
I/O Card
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Table 8. UPIO-M3U1xx Card H4 Pin Descriptions (J4)
Signal Name
Description
GND
H4_99
H4_98
H4_97
ITM_CLK
ITM_DAT3
ITM_DAT2
ITM_DAT1
ITM_DAT0
H4_91
EZR_GPIO4
EZR_GPIO3
EZR_GPIO2
EZR_GPIO1
EZR_GPIO0
EZR_VDI
EZR_ARSSI
EZR_RESET
EZR_SI100X_RX
EZR_FFIT
EZR_DTO
EZR_SI100X_TX
EZR_NFFS
EZRP_NIRQ
EZRP_SDN
GND
EZRP_RX_DATA_OUT
EZRO_RX_CLK_OUT
EZRP_TX_DATA_IN
GND
PB2.3 header
PB2.2 header
PB2.1 header
PB2.0 header
PB1.15 header
EZRP_CLK_IN
GND
EXTREG_BD_A
EXTREG_OUT_A
EXTREG_SN_A
PB1.14 header
PB3.11 header/External Voltage Regulator base drive out-
put
PB3.10 header/External Voltage Regulator OUT output
PB3.9 header/External Voltage Regulator SN input
24
Rev. 0.1