UPIO-M3U1XX Datasheet, PDF (15/28 Pages) Silicon Laboratories – The Unified Development Platform (UDP) provides a development

APPENDIX—PIN DESCRIPTIONS
UPIO-M3U1xx
I/O Card
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Table 5. UPIO-M3U1xx Card H1 Pin Descriptions (J1)
Signal Name
LPTIMER_OUT_A
LPTIMER_IN_A
LIN_RX_B
LIN_TX_B
CAN_RX_A
CAN_TX_A
EXT_DMA_TRIG1
EXT_DMA_TRIG0
EXT_DAC_TRIG1
EXT_DAC_TRIG0
EXT_ADC_TRIG1
EXT_ADC_TRIG0
EXT_INT1
EXT_INT0
WAKEUP1
WAKEUP0
PORT_MATCH1
PORT_MATCH0
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00
Description
PB4.5 header
PB3.3 header
PB2.4 header/Red DS1 LED
PB1.15 header
PB3.11/External Voltage Regulator base drive output
PB3.10/External Voltage Regulator OUT output
PB0.10H header
PB0.9H header
PB0.13 header
PB0.12 header
PB0.11 header
PB1.9H header
PB1.8H header
PB1.7H header
PB2.12 header
PB2.11 header
PB2.10 header
PB2.9 header
PB2.8 header
PB2.7 header/Blue DS4 LED
PB2.6 header/Green DS3 LED
PB2.5 header/Yellow DS2 LED
Rev. 0.1
15