UPIO-M3U1XX Datasheet, PDF (19/28 Pages) Silicon Laboratories – The Unified Development Platform (UDP) provides a development

UPIO-M3U1xx
Table 6. UPIO-M3U1xx Card H2 Pin Descriptions (J2) (Continued)
I/O Card
Pin
38
39
40
41
42
43
44
45
Signal Name
LCD_SEG12_A
LCD_SEG11_A
LCD_SEG10_A
LCD_SEG09_A
LCD_SEG08_A
LCD_SEG07_A
LCD_SEG06_A
LCD_SEG05_A
Description
46
LCD_SEG04_A
47
LCD_SEG03_A
48
LCD_SEG02_A
49
LCD_SEG01_A
50
LCD_SEG00_A
51
GND
52
EMIF_BE0B
PB3.9 header/External regulator circuit collector
53
EMIF_CS1B
PB3.8 header/External regulator circuit supply
54
EMIF_BE1B
PB3.7 header
55
EMIF_CS0B
PB3.6 header
56
EMIF_ALE
PB3.5 header
57
EMIF_OEB
PB3.4 header
58
EMIF_WRB
PB3.3 header
59
EMIF_A0
PB3.2 header
60
EMIF_A1
PB3.1 header/Joystick right
61
EMIF_A2
PB3.0 header/Joystick down
62
EMIF_A3
PB2.14 header
63
EMIF_A4
PB2.13 header
64
EMIF_A5
PB2.12 header
65
EMIF_A6
PB2.11 header
66
EMIF_A7
PB2.10 header
67
EMIF_A8
PB2.9 header
68
EMIF_A9
PB2.8 header
69
EMIF_A10
PB2.7 header
70
EMIF_A11
PB2.6 header
71
EMIF_A12
PB2.5 header
72
EMIF_A13
PB2.4 header
73
EMIF_A14
PB2.3 header
74
EMIF_A15
PB2.2 header
Rev. 0.1
19