HYB39S13620TQ- Datasheet, PDF (8/70 Pages) Siemens Semiconductor Group – Special Mode Registers Two color registers Burst Read with Single Write Operation

HYB 39S16320TQ-6/-7/-8
Functional Description
General
The 16 Mbyte SGRAM is a dual bank 1024 × 256 × 32 DRAM with graphics features of Block Write
and Masked Write. It consists of two banks. Each bank is organized as 1024 rows
× 256 columns × 32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate
command which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and the row to be accessed. BA
selects the bank and address bits A9 - A0 select the row. Address bits A7 - A0 registered coincident
with the Read or Write command are used to select the starting column location for the burst
access.
Block Writes are not burst oriented and always apply to eight column locations selected by A7 - A3.
DQs registered at Block Write command are used to mask the selected columns. DQs registered
coincident with the Load Special Mode Register command are used as Color Data (LC-Bit = 1) or
Persistent Mask (LM = 1). If LC and LM are both 1 in the same Load Special Mode Register
command cycle, the data of the Mask and the Color Register will be unknown.
Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees, that the device is preconditioned to each
users specific needs.
The following sequence is recommended:
• During power on, all V_DD and V_DDQ pins must be built up simultaneously to the specified voltage
when the input signals are held in the “NOP” state.
• The power on voltage must not exceed V_DD + 0.3 V on any of the input pins or V_DD supplies.
• The CLK signal must be started at the same time.
• After power on, an initial pause of 200 µs is required.
• The pause is followed by a precharge of both banks using the precharge command.
• To prevent data contention on the DQ bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause period.
• Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register.
• A minimum of eight Auto Refresh cycles (CBR) are also required.
It is also possible to reverse the last two steps of the initialization procedure:
First send at least 8 CBR commands, then the LMR command.
Failure to follow these steps may lead to unpredictable start-up modes.
Semiconductor Group
8
1998-10-01