HYB39S13620TQ- Datasheet, PDF (12/70 Pages) Siemens Semiconductor Group – Special Mode Registers Two color registers Burst Read with Single Write Operation

HYB 39S16320TQ-6/-7/-8
Notes
1. All inputs are latched on the rising edge of the CLK.
2. LMR, REF and SREF commands should be issued only after both banks are deactivated
(PREAL command).
3. ACT and ACTM command should be issued only after the corresponding bank has been
deactivated (PRE command).
4. WR, WRA, RD, RDA should be issued after the corresponding bank has been activated
(ACT command).
5. Auto Precharge command is not valid for full-page burst.
6. BW and BWA commands use mask register data only after ACTM command. DQM byte masking
is active regardless of WPB mask.
7. Loading Mask Register: Initiate an LSMR cycle with address pin A5 = 1 to load the mask register
with the mask data present on DQ pins. Except A5, all other address pins must be “0” during
LSMR cycle while loading the mask register.
8. Loading Color Register: Initiate an LSMR cycle with address pin A6 = 1 to load the color register
with the color input data on DQ pins. Address pin A7 selects color register. Except A6 and A7, all
other address pins must be “0” during LSMR cycle while loading a color register. If one color
register mode is enabled, all address pins, except A6, must be “0” during LSMR cycle.
9. If BW or BWA operation is initiated and 2-Color Register Mode is initialized by the mode register,
address A0 selects the desired color register for the operation. If A0 = 0, color register 0 will be
used, if A0 = 1, color register 1.
10.Any Write or Block Write cycles to the selected bank/row while active will be masked according
to the contents of the mask register, in addition to the DQM signals and the column/byte mask
information (the later for Block Writes only).
11.Block Writes are not burst oriented and always apply to the eight column locations selected by
A7 - A3.
12.Addressline A9 is always “X” with the exception of two commands:
In LMR and LSMR commands it provides opcode (see description Mode and Special Mode
Register). In ACT and ACTM commands it provides the address bit 9 of the row address.
Semiconductor Group
12
1998-10-01