HYB39S13620TQ- Datasheet, PDF (17/70 Pages) Siemens Semiconductor Group – Special Mode Registers Two color registers Burst Read with Single Write Operation

HYB 39S16320TQ-6/-7/-8
Precharge (PRE)
The Precharge command is used to deactivate the open row in a particular bank or the open row in
both banks. The bank(s) will be available for row access some specified time (t_RP) after the
Precharge command is issued. Input A8 determines whether one or both banks are to be
precharged, input BA selects the bank. If A8 is “1”, both banks are to be precharged and BA is “don't
care.” Once a bank is precharged (or deactivated), it is in the idle state and must be activated prior
to any Read, Write, or Block Write commands being issued to that bank.
Auto Precharge (PREA)
The Auto Precharge feature allows the user to issue a Read, Write, or Block Write command that
automatically performs a precharge upon the completion of the Block Write access or Read or Write
burst, except in the Full Page Burst mode, where it has no effect. The use of this feature eliminates
the need to “manually” issue a Precharge command during the functional operation of the SGRAM.
Burst Terminate (BST)
The Burst Terminate command is used to truncate either fixed-length or Full Page Bursts.
Auto Refresh (REF)
Auto Refresh is used to refresh the various rows in the SGRAM and is analogous to CAS-before-
RAS (CBR) in DRAMs. This command must be issued each time a refresh is required. The
addressing is generated by the internal refresh counter, therefore, the address bits are “don't care”
during a CBR cycle. The SGRAM requires that 2048 rows to be refreshed every 32 ms (t_REF). This
refresh can be accomplished either by providing an Auto Refresh command every 15.6 µs or all
2048 Auto Refresh commands can be issued in a burst at the minimum cycle rate (t_RC) once every
32 ms.
Self Refresh (SREF)
The Self Refresh command can be used to retain data in the SGRAM, even if the rest of the system
is powered down. When in the Self Refresh mode, the SGRAM retains data without external
clocking. Once the SREF command is registered, all the inputs to the SGRAM become “don't care”
with the exception of CKE, which must remain low. Once SREF mode is engaged, the SGRAM
provides its own internal clocking, causing it to perform its own Auto Refresh cycles. The SGRAM
may remain in Self Refresh mode for an indefinite period. The procedure for exiting requires a
sequence of commands. First, the system clock must be stable prior to CKE going high. Once CKE
is high, the SGRAM must have NOP commands issued for t_SRX, because of the time required for the
completion of any bank currently being internally refreshed.
Semiconductor Group
17
1998-10-01