HYB39S13620TQ- Datasheet, PDF(19/70 Page) Siemens Semiconductor Group – Special Mode Registers Two color registers Burst Read with Single Write Operation

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HYB39S13620TQ- Datasheet, PDF (19/70 Pages) Siemens Semiconductor Group – Special Mode Registers Two color registers Burst Read with Single Write Operation

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HYB 39S16320TQ-6/-7/-8

A fixed-length Write burst may be followed by, or truncated with a Precharge command to the same

bank (provided that Auto Precharge was not activated) and a full-page Write burst may be truncated

with a Precharge command to the same bank. The Precharge command should be issued x cycles

(x = tWR/tCK rounded up to the next whole number) after the clock edge at which the last desired

input data element is registered. In addition, the DQM signals must be used to mask input data,

starting with the clock edge following the last desired data element and ending with the clock edge

on which the Precharge command is entered. A Precharge command issued at the optimum time

provides the same operation that would result from the same fixed-length Burst with Auto

Precharge.

Disadvantages of Write Command with Auto Precharge

1. Back to back Read/Write bursts can not be initiated. The Read/Write command with Auto

Precharge will automatically initiate a precharge of the row in the selected bank. Most of the

applications require subsequent Read/Write bursts in the same page.

2. The Auto Precharge command does not allow truncation of fixed-length bursts. It also does not

apply to Full Page bursts.

Terminating a Write Burst

The fixed-length or Full-Page Write bursts can be truncated with the Burst Terminate command.

When truncating a Write burst, the input data applied one clock edge prior to the Burst Terminate

command will be the last data written.

Masked Writes

Any Write performed to a row that was activated via an Active with WPB command is a Write-per-

Bit-Mask (WPBM). Data is written to the 32 cells at the selected column location subject to the mask

stored in the WPB mask register. The data to be written in the DRAM cell will be according to the

following mask:

Write Masking Function Representation

DQM

DRAM Cell

Mask

Write

Semiconductor Group

1998-10-01

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