SDA9254-2 Datasheet, PDF (7/32 Pages) Siemens Semiconductor Group – 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter

SDA 9254-2
Write Transfer from Latch C to Memory (RE)
The data of latch C are transferred to the preaddressed location of the memory array at the rising
edge of RE, if the mode bits were set to H (M1) and L (M0), see “Addressing and Mode Control.”
Addressing and Mode Control (SAR, SAC, SCAD, RE)
The serial 8-bit row address SAR and the 8-bit column address/mode code SAC are serially shifted
into the TV-SAM (LSB first) at rising edge of the address clock SCAD. After 8 SCAD cycles, the
falling edge of RE internally latches SAR and SAC. The column address itself needs only 6 bits. The
last 2 bits of SAC are defined as mode bits and determine the read/write and refresh operation of
the memory arrays to be triggered by the RE signal.
Mode Bit M1
L
L
H
H
Mode Bit M0
L
H
L
H
Operation
Read transfer from memory to latch A
Read transfer from memory to latch B
Write transfer from latch C to memory
Refresh with internal row address
Read Transfer from Memory to Latch A or B (RE)
Memory data from a preaddressed location are transferred to latch A or B at the falling edge of RE,
depending on the mode control bits, see “Addressing and Mode Control”.
Data Transfer from Latch A to Shift Register A (RA)
The data of latch A are transferred to shift register A at the falling edge of the read transfer signal
RA. If the timing restrictions between RA and the shift clock SCA are taken into account, a
continuous data flow at output SQA without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch A transfer.
Data Transfer from Latch B to Shift Register B (RB)
The data of latch B are transferred to shift register B at the falling edge of the read transfer signal
RB. If the timing restrictions between RB and the shift clock SCB are taken into account, a
continuous data flow at memory output port B without interrupts is possible. This transfer operation
is independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch B transfer.
For correct operation of the recursive filtering the memory output data at port B must be in phase
with the input data SDC. This restriction forces a fixed space of time between RB and WT of 25
clock periods of SCB (see diagram 8).
Semiconductor Group
7
1998-01-16