SDA9254-2 Datasheet, PDF (6/32 Pages) Siemens Semiconductor Group – 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter

SDA 9254-2
Circuit Description
Memory Architecture
As shown in the block diagram of the memory part (see figure 7), the TV-SAM comprises 192
memory arrays, which are accessed in parallel. Each memory array has a size of 212 rows by 64
columns. The rows and columns of the 192 arrays can be randomly addressed, reading or writing
16 x 12 bits at a time. To obtain the extremely high data rate at the 12-bit wide data input (port C)
and outputs (port A and B), a parallel to serial conversion is done using shift registers of 16-bit
length and 12-bit width. In this way the memory speed is increased by a factor of 16. (This is
independent on the number of ports if the total data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 x 12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.
Data Input (SDC, SCB)
The data pins SDC are connected to the input of the recursive filter. The delay time from SDC to
the memory port C caused by the filter amounts 8 periods of the clock SCB. The delay time is to be
considered for the generation of the signal WT (see diagram 8).
Data are shifted into the memory using the serial port C at the rising edge of the shift clock SCB.
After 16 clock pulses the data have to be transferred from shift register C to latch C. If more than
16 clock pulses occur before latching the data, only the last sixteen 12-bit data values are accepted.
Data Input (DLI), Data Output (DLO, OEDLO)
In 4:2:2-mode 4 bitplanes of the chrominance signals are connected to an internal delay line via the
pins DLI. After 8 periods of clock SCB the input data are supplied at the delay line output DLO.
Via the output enable OEDLO the output buffers can be switched into tristate. In 4:1:1-mode the DLI
pins should be connected to GND and pin OEDLO should be connected to V_DD.
Data Transfer from Shift Register C to Latch C (WT)
The contents of the shift register C is transferred to latch C at the falling edge of the write transfer
signal WT. If the timing restrictions between WT and the clock SCB are respected, a continuous
data flow at input port C is possible without loosing data. This transfer operation may be
asynchronous to all other transfer operations except for a small forbidden window conditioned by
the latch C to memory transfer, see diagram 4.
Semiconductor Group
6
1998-01-16