SDA9254-2 Datasheet, PDF (5/32 Pages) Siemens Semiconductor Group – 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter

SDA 9254-2
The following diagram shows the requested data format for 4:1:1 signals at the input
SDC0 … SDC11. The output data format at pins SQA0 … SQA11 corresponds to the input format.
BLN
13.5 MHz
SDC 4 ... 11
SDC 3
SDC 2
SDC 1
SDC 0
Y1
Y2
Y3
Y4
Y5
Y6
U1,7
U1,5
U1,3
U1,1
U2,7
U2,5
U1,6
U1,4
U1,2
U1,0
U2,6
U2,4
V1,7
V1,5
V1,3
V1,1
V2,7
V2,5
V1,6
V1,4
V1,2
V1,0
V2,6
V2,4
UED08600
Figure 4
Input Data Format (4:1:1)
Memory
The memory has a capacity of 2605056 bit. It is organized as 212 rows by 64 columns by 16 arrays
by 12 bit and allows the storage of the active part of a complete 4:1:1-TV field using a 13.5 MHz
sample rate. The memory is fabricated using the same CMOS technology used for 4-Mbit standard
dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 12-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column address
(SAC) which contains the desired column address and an instruction code (mode bits) for transfer
and refresh.
Semiconductor Group
5
1998-01-16