SDA9288X Datasheet, PDF (44/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
4.3.2 Phase Relation of Sync Pulses at Frame Mode
If the phase relation is not correct at the H and V sync inputs, an adjustment via bits
VSIDEL and VSPDEL is possible.
Figure 12
Signal Flow of the Horizontal Synchronization (insert part)
Figure 13
Allowed Phase Relation of the
Horizontal/Vertical Sync Pulses (insert channel) if VSIDEL(0:4) = ‘0000’
Semiconductor Group
44
03.96