SDA9288X Datasheet, PDF (23/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
Bit
Name
Function
Subaddress 05
D1 … D0 IMOD
D3 … D2 PMOD
D4
CHRINS
D5
INSHVI
D6
DECHOR
D7
DECVER
00: automatic detection of line standard (inset signal)
01: fixed adjustment 625 lines¹⁾
10: fixed adjustment 525 lines¹⁾
11: freeze last line standard
00: automatic detection of line standard (parent signal)
01: fixed adjustment 625 lines¹⁾
10: fixed adjustment 525 lines¹⁾
11: freeze last line standard
0: chrominance input signals + (B-Y), + (R-Y)
1: inverted chrominance input signals – (B-Y), – (R-Y)
0: inset synchronization signals via pins HPD/SCI
and VPD/VI
1: inset synchr. signals via pin HVI (3-I. sand-castle signal)
0: horizontal decimation 3 to 1
1: horizontal decimation 4 to 1
0: vertical decimation 3 to 1
1: vertical decimation 4 to 1
Subaddress 06
D3 … D0 HSIDEL
Delay of horizontal synchronization pulse (inset signal)
Raster: 6 clock periods of 13.5 MHz.
Warning: Adjustment of HSIDEL will influence the adjustment
of VSIDEL (subaddr. 07); see chapter 4.3
D4
CLISW 0: inset clock synchronized with parent clock
1: inset clock synchronized with quartz frequency
Note: Only one of the two modes can be used.
Switching back from ‘1’ to ‘0’ is not possible!
D5
CLPFIX 0: clamp pulses of ADC are dependent on the adjustment
of HSIDEL
1: clamp pulses fixed; no influence of HSIDEL
D6
CLPS
0: three clamp cycles per line (timing see diagram)
1: two clamp cycles per line
1) _{Fixed adjustments for IMOD and PMOD result in undefined working conditions when signal standards are}
used which are different from the programmed values.
Semiconductor Group
23
03.96