SDA9288X Datasheet, PDF (24/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
Bit
Name
Function
Subaddress 07
D4 … D0 VSIDEL
D5
VSIISQ
D7
AMSEC
Delay of vertical synchronization pulse (inset signal)
in steps of 2.37 µs.
Warning: Correct adjustment value is influenced by the
adjustment of HSIDEL (subaddr. 06); see chapter 4.3.
Noise reduction of the VSI pulse
(set to ‘0’ under normal conditions)
0: unity amplification of decimation filters (normal mode)
1: amplification by a factor of 2 (SECAM signals without delay
line in the chroma decoder)
Subaddress 08
D4 … D0 VSPDEL Delay of vertical synchronization pulse (parent signal)
in steps of 2.37 µs/1.68 s (50/100 Hz)
D5
VSPISQ Noise reduction of the VSP pulse (should be set to ‘0’ under
normal conditions); in case changing from standard mode to
line or frame conversion modes ‘1’ should be set during the
changement of line frequency
D7
PARSYND 0: parent synchronization signals for double frequency read
via pins HP/SCP and VP
1: parent synchronization signals for double frequency read
via pins HPD/SCI and VPD/VI (INSHVI = ‘1’ required)
Subaddress 09
D3 … D0 FRY
D7 … D4 CON
Luminance component of frame color (4 MSBs of 6 bit)
Contrast adjustment of PIP picture; steps and adjustment
range depending on the external output resistors.
Proposed value see chapter 3.3
Subaddress 0A
D3 … D0 FRU
D7 … D4 FRV
Chrominance component (B-Y) of frame color
(4 MSBs of 6 bit)
Chrominance component (R-Y) of frame color
(4 MSBs of 6 bit)
Semiconductor Group
24
03.96