SDA9288X Datasheet, PDF (12/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
2
System Description
2.1 AD Conversion, Inset Synchronization
The inset video signal is fed to the SDA 9288X A141 as analog luminance and
chrominance components¹⁾. The polarity of the chrominance signals is programmable.
After clamping the video components are AD-converted with an amplitude resolution of
6 bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a
3.375 MHz clock for the chrominance signals.
For the adaption to different application the clamp timing for the analog inputs can be
chosen (CLPS; CLPFIX). Setting this bits to ‘1’ can be useful for non-standard input
signals.
For inset synchronization it is possible to feed either a special 3-level signal via pin HVI
(detection of horizontal and vertical pulses) or separate signals via pins SCI for
horizontal and VI for vertical synchronization. SCI is the horizontal synchron signal of the
inset channel. If the burst gate pulse of the sandcastle is used it must be adapted to
TTL compatible levels by a simple external circuit. Centering of the displayed picture
area is possible by a programmable delay for the horizontal synchronization signal
(HSIDEL).
The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz
clock and the AD converter clocks are derived from the parent horizontal synchronization
pulse (see chapter 2.6) or from the quartz frequency converted by a factor of 4/3.
Delay differences between luminance and chrominance signals at the input of the IC
caused by chroma decoding are compensated by a programmable luminance delay
line (YDEL) of about – 290 ns … 740 ns (at decimation input; see Application
Information).
By analyzing the synchronization pulses the line standard of the inset signal source is
detected and interference noise on the vertical sync signal is removed. For applications
with fixed line standard (only 625 lines or 525 lines) the automatic detection can be
switched off.
The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way
a correct detection of the field number is possible, an important condition for frame mode
display.
Note: The adjustment of VSIDEL is influenced by HSIDEL (see chapter 4.3), vertical
synchronization via pin HVI causes an additional internal delay for the vertical
sync pulse of about 16 µs.
1) _{To improve the signal-to-noise ratio the amplitude of the input signals should be as large as possible.}
Semiconductor Group
12
03.96