SDA9288X Datasheet, PDF (29/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
3.2 Operational Range (cont’d)
Parameter
Symbol
Limit Values
Unit Remark
min. typ. max.
Quartz/Ceramic Resonator²⁾
Recommended
frequency
Series resistance
20.25 20.48 21.3
10
20
30
40
MHz 21.09 MHz for MUSE
Ω C₁, C₂ ≤ 33 pF
Ω C₁, C₂ ≤ 22 pF
Ω C₁, C₂ ≤ 15 pF
Ω C₁, C₂ ≤ 10 pF
(total series
capacitance)
Optional TTL Clock Input: XIN¹⁾
Clock input cycle time
35
Clock input rise time
Clock input fall time
Clock input low time
10
Clock input high time
10
40
ns External line locked;
5
ns ^{27 MHz clock}
(I²C: internal PLL
5
ns _OFF)
ns
ns
Fast I²C Bus^{1) 3)}
SCL clock frequency f_SCL
0
Inactive time before t_BUF
1.3
start of transmission
400 kHz
µs
Setup time
t_{SU; STA} 0.6
µs
start condition
Hold time start
t_{HD; STA} 0.6
µs
condition
SCL low time
t_LOW
1.3
µs
1) _{All values are referred to min (VIH) and max (VIL).}
2) _{There is no internal protection for the crystal driver against oscillation at harmonic frequencies.}
3) _{This specification of the bus lines does not have to be identical with the I/O stages specification because of}
optional series resistors between bus lines and I/O pins.
Semiconductor Group
29
03.96