SDA9288X Datasheet, PDF (21/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
Bit
Name
Function
Subaddress 00
D0
PIPON
D1
FRAME
D2
LINEDBL
D3
READ27
D4
PLLOFF
D5
FREEZE
D6
SYSACT
0: PIP insertion OFF
1: PIP insertion ON
0: field display
1: frame display (under special restrictions).
Correct adjustment of bits VSIDEL, VSPDEL required
(see chapter 4.3)
0: each line of the PIP memory is read once
(normal operation)
1: each line of the PIP memory is read twice
(line doubling for progressive scan conversion systems
in parent channel)
0: PIP display with single read frequency (13.5 MHz)
1: PIP display with double read frequency (27 MHz)
(see note page 19).
0: internal PLL ON
1: internal PLL OFF (external clock generation)
0: live picture
1: freeze picture
0: pin SYS inactive: selection of decimation amplification and
RGB-matrix is done via I²C Bus
1: pin SYS active: selection of decimation amplification
and RGB-matrix is done via pin SYS
Subaddress 01
D1 … D0 POSHOR
D2
MIXDIS
D6 … D3 SELDEL
2 MSBs of POSHOR (see also subaddress 02)
0: PIP picture height depends just upon inset line standard,
position upon POSHOR
1: modified PIP picture height and position for different inset
and parent line standards (mixed display mode)
Delay of output signal SELECT at pins SEL respectively SELD
(– 8 … 7 periods of read frequency clock, programmable in
2’s complement code). SELDEL = ‘0’: SELECT signal has the
same phase as the PIP picture signal referenced to the
IC output.
Semiconductor Group
21
03.96