SDA9288X Datasheet, PDF (19/46 Pages) Siemens Semiconductor Group – Single Chip PIP System

SDA 9288X
2.5 DA Conversion
The SDA 9288X A141 includes three 6-bit DA converters. Each converter supplies a
current through an external resistor that is connected between V_SSA and OUT1, OUT2,
OUT3 respectively. The current is controlled by a digital control circuit. Each command
DACONST or PIPON starts the adjustment cycle.
2.6 PLL
A numerical PLL circuit supplies a clock of about 27 MHz with high stability. The
generated clock is locked to the parent horizontal synchronization pulse. Its frequency
depends linearly on the frequency of the sync signal and the quartz frequency. The
recommended quartz frequencies are listed under ‘Recommended Operation
Conditions’. Using up to three SDA 9288X A141 ICs in one application only a single
quartz is necessary. Four time constants are programmable via I²C Bus. If the PLL is
switched off an external 27 MHz parent line locked clock can be fed to the IC.
The inset clock generation is possible in two ways:
1. Synchron with the parent horizontal synchronization pulse (bit CLISW = ‘0’)
2. Synchron with the quartz frequency (bit CLISW = ‘1’; f_cli = 4/3 × f_quartz). In this mode the
aspect ratio is independent on the parent sync frequency but depends on the used
resonator type. It is only possible to use one of the two modes.
Note: Before setting bit D3 of subaddress 00 (READ27) noise reduction of the
VSP pulse must be switched off (D5 of subaddress 08 = ‘1’).
2.7 I²C Bus
2.7.1 I²C Bus Addresses
Three different I²C addresses are programmable via pin ADR.
Pin ADR
Low level (V_SS or V_SSA)
Mid level (open)
High level (V_DD or V_DDA)
Address (bin.)
11010110
11011100
11011110
Address (hex.)
D6
DC
DE
2.7.2 I²C Bus Receiver Format
S
Address
A Subaddress A Data Byte A ****
AP
S: start condition
A: acknowledge
P: stop condition
Only write operation is possible. An automatically address increment function is
implemented.
Semiconductor Group
19
03.96