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HYB511000BJ- Datasheet, PDF (10/22 Pages) Siemens Semiconductor Group – 1 M x 1-Bit Dynamic RAM Low Power 1 M ´ 1-Bit Dynamic RAM
HYB 511000BJ/BJL-50/-60/-70
1 M × 1-DRAM
Notes :
1) All voltages are referenced to VSS .
2) ICC1 , ICC3 , ICC4, ICC6, ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles before proper device operation
is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL .
6) Measured with a load equivalent to 2 TTL loads and 100 pF.
7) tOFF (max.) defines the time at which the output achieves the open-circuit conditions and is not referenced to
output voltage levels.
8) Either tRCH or tRRH must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
in read-write cycles.
10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only.
If tWCS ≥ tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle; if tRWD ≥ tRWD (min.), tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-write
cycle and DO will contain data read from the selected cell. If neither of the above sets of conditions is satisfied,
the condition of DO (at access time) is indeterminate.
11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC .
12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA .
13) AC measurements assume tT = 5ns.
Semiconductor Group
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