GS2972 Datasheet, PDF (82/125 Pages) Semtech Corporation – 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support

4.11 Serial Clock PLL
An internal VCO provides the transmission clock rates for the GS2972.
The power supply to the VCO is provided to the VCO_VDD/VCO_GND pins of the
device.
This VCO is locked to the input PCLK via an on-chip PLL and Charge Pump.
Internal division ratios for the PCLK are determined by the setting of the RATE_SEL0 pin,
the RATE_SEL1 pin and the 20BIT/10BIT pin as shown in Table 4-25:
Table 4-25: PCLK and Serial Digital Clock Rates
External Pin Setting
RATE_SEL0
RATE_SEL1
20BIT/10BIT
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
X
LOW
HIGH
LOW
HIGH
LOW
Supplied
PCLK Rate
Serial Digital
Output Rate
148.5 or
2.97 or
148.5/1.001MHz 2.97/1.001 Gb/s
148.5 or
148.5/1.001MHz
(DDR)
2.97 or
2.97/1.001 Gb/s
74.25 or
1.485 or
74.25/1.001MHz 1.485/1.001Gb/s
148.5 or
1.485 or
148.5/1.001MHz 1.485/1.001Gb/s
13.5MHz
270Mb/s
27MHz
270Mb/s
As well as generating the serial digital output clock signals, the PLL is also responsible
for generating all internal clock signals required by the device.
4.11.1 PLL Bandwidth
Table 4-26 shows the GS2972 PLL loop bandwidth variations. PLL bandwidth is a
function of the external loop filter resistor and the charge pump current. We
recommend using a 200Ω loop filter resistor, however, this value can be varied from
100Ω to 380Ω, depending on application. Values other than 200Ω are not guaranteed.
As the resistor is changed, the bandwidth will scale proportionately (for example, a
change from a 200Ω to 300Ω resistor will cause a 50% increase in bandwidth). The
charge pump current is preset to 100μA and should not be changed. The external loop
filter capacitor does not affect the PLL loop bandwidth. The external loop filter capacitor
affects PLL loop settling time, phase margin and noise. It is selectable from 1μF to 33μF.
However, it should be kept at 10μF for optimal performance. A smaller capacitor results
in shorter lock time but less stability. A larger capacitor results in longer lock time but
more stability. Narrower loop bandwidths require a larger capacitor to be stable. In other
words, a small loop filter resistor requires a larger loop capacitor.
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
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