GS2972 Datasheet, PDF (31/125 Pages) Semtech Corporation – 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support

4.2 Parallel Data Inputs
Data signal inputs enter the device on the rising edge of PCLK, as shown in Figure 4-1.
DDR interface
Note: DS = Data Stream as per SMPTE ST 425
3.36ns
PCLK
TH
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
DS1_n-1
transition zone
DS2_* is launched on the
negative edge of PCLK
by the source chip to the
GS2972
DS1_* is launched on the
positive edge of PCLK
by the source chip to the
GS2972
TSU
TH
DS1_n-1
DS2_0
transition zone
TSU
TH
DS2_0
DS1_0
transition zone
DS1_0
SDR interface
DS* is launched on the positive edge of PCLK
by the source chip to the GS2972
PCLK period
PCLK
TH
DIN[19:0], F_DE,
H_HSYNC, V_VSYNC
data_0
transition zone
TSU
TH
data_0
Figure 4-1: GS2972 Video Host Interface Timing Diagrams
data_1
transition zone
TSU
TH
data_1
Table 4-1: GS2972 Digital Input AC Electrical Characteristics
Parameter
Input data set-up time
Input data hold time
Input data set-up time
Input data hold time
Symbol
t_SU
t_IH
t_SU
t_IH
Conditions
50% levels;
+1.8V operation
50% levels;
+3.3V operation
Min
Typ
Max
1.2
-
-
0.8
-
-
1.3
-
-
0.8
-
-
Units
ns
ns
ns
ns
Table 4-2: GS2972 Input Video Data Format Selections
Input Data Format
20-bit demultiplexed 3G
format
20-bit data Input
3G format
20-bit demultiplexed
HD format
20BIT
/10BIT
HIGH
HIGH
HIGH
Pin/Register Bit Settings
RATE
_SEL0
RATE
_SEL1
SMPTE
_BYPASS
DVB_ASI
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
DIN[9:0]
Data Stream
Two
DATA
Chroma
DIN[19:10]
Data Stream One
DATA
Luma
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
31 of 125