GS2972 Datasheet, PDF (12/125 Pages) Semtech Corporation – 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support

Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
A4
H/HSYNC
A5, E1, G10,
K8
A6, B6
A7
A8
A9, D6, D7,
D8, F4
A10
CORE_VDD
PLL_VDD
LF
VBG
RSV
A_VDD
B4
PCLK
B5, C5, E2,
E5, E6, F5,
F6, G9
CORE_GND
Timing
Type
Description
Synch-
ronous
with
PCLK
Input
PARALLEL DATA TIMING.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
TIM_861 is LOW:
The H signal is used to indicate the portion of the video line
containing active video data, when DETECT_TRS is set LOW.
Active Line Blanking
The H signal should be LOW for the active portion of the video line.
The signal goes LOW at the first active pixel of the line, and then
goes HIGH after the last active pixel of the line.
The H signal should be set HIGH for the entire horizontal blanking
period, including both EAV and SAV TRS words, and LOW otherwise.
TRS Based Blanking (H_CONFIG = 1_h)
The H signal should be set HIGH for the entire horizontal blanking
period as indicated by the H bit in the received TRS ID words, and
LOW otherwise.
TIM_861 = HIGH:
The HSYNC signal indicates horizontal timing. See Section 4.3.
When DETECT_TRS is HIGH, this pin is ignored at all times.
If DETECT_TRS is set HIGH and TIM_861 is set HIGH, the DETECT_TRS
feature will take priority.
Input Power
Power supply connection for digital core logic. Connect to +1.2V DC
digital.
Input Power Power supply pin for PLL. Connect to +1.2V DC analog.
Analog
Output
Loop Filter component connection.
Output
Bandgap voltage filter connection.
−
These pins are reserved and should be left unconnected.
Input Power VDD for sensitive analog circuitry. Connect to +3.3VDC analog.
PARALLEL DATA BUS CLOCK.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
3G 20-bit mode
PCLK @ 148.5MHz
Input
3G 10-bit mode DDR
HD 20-bit mode
PCLK @ 148.5MHz
PCLK @ 74.25MHz
HD 10-bit mode
PCLK @ 148.5MHz
SD 20-bit mode
PCLK @ 13.5MHz
SD 10-bit mode
PCLK @ 27MHz
DVB-ASI mode
PCLK @ 27MHz
Input Power GND connection for digital logic. Connect to digital GND.
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
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