GS2972 Datasheet, PDF (78/125 Pages) Semtech Corporation – 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support

4.9.9 Line Based CRC Generation and Insertion (HD/3G)
When operating in HD mode (RATE_SEL0 pin = LOW, RATE_SEL1 pin = LOW), the
GS2972 generates and inserts line based CRC words into both the Y and C channels of
the data stream.
When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level A mode,
the GS2972 generates and inserts line based CRC words into both Data Stream One and
Data Stream Two.
When operating in 3G (RATE_SEL0 pin = LOW, RATE_SEL1 pin = HIGH) Level B mode,
the GS2972 generates and inserts line based CRC words into both Y and C channels of
both Link A and Link B.
The line based CRC insertion only takes place if the IOPROC_EN/DIS pin is HIGH and
SMPTE_BYPASS is HIGH.
In addition to this, the GS2972 requires the EDH_CRC_INS bit to be set LOW in the
IOPROC register.
4.9.10 EDH Generation and Insertion
When operating in SD mode, the GS2972 generates and inserts EDH packets into the
data stream.
The EDH packet generation and insertion only takes place if the IOPROC_EN/DIS pin is
HIGH, SMPTE_BYPASS pin is HIGH, the RATE_SEL0 pin is HIGH and the EDH_CRC_INS
bit is set LOW in the IOPROC register.
Calculation of both Full Field (FF) and Active Picture (AP) CRCs is carried out by the
device.
EDH error flags EDH, EDA, IDH, IDA and UES for ancillary data, full field and active
picture are also inserted.
• When the EDH_CRC_UPDATE bit of the host interface is set LOW, these flags are
sourced from the ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers of
the device, where they are programmed by the application layer
• When the EDH_CRC_UPDATE bit of the host interface is set HIGH, incoming EDH
flags are preserved and inserted in the outgoing EDH packets. In this mode the
ANC_EDH_FLAG, FF_EDH_FLAG and AP_EDH_FLAG registers contain the
incoming EDH flags, and will be read only
The GS2972 generates all of the required EDH packet data including all ancillary data
preambles: DID, DBN, DC, reserved code words and checksum.
The prepared EDH packet is inserted at the appropriate line of the video stream (in
accordance with RP165). The start pixel position of the inserted packet is based on the
SAV position of that line, such that the last byte of the EDH packet (the checksum) is
placed in the sample immediately preceding the start of the SAV TRS word.
Note 1: When the EDH_CRC_UPDATE bit of the host interface is set LOW, it is the
responsibility of the application interface to ensure that the EDH flag registers are
updated regularly (once per field).
Note 2: It is also the responsibility of the application interface to ensure that there is
sufficient space in the horizontal blanking interval for the EDH packet to be inserted.
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
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