GS2972 Datasheet, PDF (15/125 Pages) Semtech Corporation – 3G/HD/SD-SDI Serializer with Complete SMPTE Audio & Video Support

Table 1-1: Pin Descriptions (Continued)
Pin
Number
F3
F8
F10
G1, H10
G2, H9
G3
G4
G5
Name
DETECT_TRS
TDO
RSET
IO_VDD
IO_GND
TIM_861
20BIT/10BIT
DVB_ASI
Timing
Type
Description
Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select external HVF timing mode or TRS extraction timing
mode.
When DETECT_TRS is LOW, the device extracts all internal timing
from the supplied H:V:F or CEA-861 timing signals, dependent on
the status of the TIM861 pin.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
Output
COMMUNICATION SIGNAL OUTPUT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Dedicated JTAG pin.
JTAG Test Data Output.
This pin is used to shift results from the device when the JTAG/HOST
pin is LOW.
Input
An external 1% resistor connected to this input is used to set the
SDO/SDO output signal amplitude.
Input Power
Power connection for digital I/O. Connect to +3.3V or +1.8V DC
digital.
Input Power Ground connection for digital I/O. Connect to digital GND.
Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select external CEA-861 timing mode.
When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts
all internal timing from the supplied H:V:F timing signals.
When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts
all internal timing from the supplied HSYNC, VSYNC, DE timing
signals.
When DETECT_TRS is HIGH, the device extracts all internal timing
from TRS signals embedded in the supplied video stream.
Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to select the input bus width.
Input
CONTROL SIGNAL INPUT.
Please refer to the Input Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Used to enable/disable the DVB-ASI data transmission.
When DVB_ASI is set HIGH and SMPTE_BYPASS is set LOW, then the
device will carry out DVB-ASI word alignment, I/O processing and
transmission.
When SMPTE_BYPASS and DVB_ASI are both set LOW, the device
operates in data-through mode.
GS2972 3G/HD/SD-SDI Serializer with Complete
SMPTE Audio & Video Support
Final Data Sheet Rev. 9
GENDOC-047479 September 2013
www.semtech.com
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