LC875CC8A Datasheet, PDF (23/29 Pages) Sanyo Semicon Device – ROM 128K/112K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller

LC875CC8A/B2A
Continued from preceding page.
Parameter
Symbol
Pins/
Remarks
Conditions
VDD[V]
min
HALT mode
consumption
current
(Note 7-1)
IDDHALT(1)
IDDHALT(2)
VDD1
=VDD2
=VDD3
=VDD4
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
4.5 to 5.5
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
2.8 to 5.5
Specification
typ
max unit
3.3
6
1.6
3.5
• 1/1 frequency division ratio.
IDDHALT(3)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
2.3
4.5
mode
IDDHALT(4)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
2.5 to 5.5
0.98
2.5
• 1/1 frequency division ratio.
IDDHALT(5)
• HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
1.2
2.0
mode
mA
IDDHALT(6)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
2.2 to 4.5
0.6
1.5
• 1/2 frequency division ratio.
IDDHALT(7)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
0.3
1
IDDHALT(8)
mode
• System clock set to internal RC oscillation
• Frequency variable RC oscillation stopped
2.2 to 4.5
0.14
0.5
•1/2 frequency division ratio.
IDDHALT(9)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
4.5 to 5.5
1.0
2.5
mode.
IDDHALT(10)
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
2.2 to 4.5
0.5
1.8
• 1/2 frequency division ratio.
IDDHALT(11)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FmX'al=32.768kHz by crystal oscillation
4.5 to 5.5
17
55
mode.
IDDHALT(12)
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
2.2 to 4.5
5
30
• 1/2 frequency division ratio.
μA
Current drain
during HOLD
mode
IDDHOLD(1)
IDDHOLD(2)
VDD1
• HOLD mode
• CF1=VDD or open (External clock mode)
4.5 to 5.5
2.2 to 4.5
0.02
10
0.008
8
Current drain
during time-
base clock
HOLD mode
IDDHOLD(3)
IDDHOLD(4)
• Timer HOLD mode
• CF1=VDD or open(External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
14
40
3.2
2.5
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A0744-23/29