K4S160822D Datasheet, PDF (8/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

K4S160822D
CMOS SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CAS latency=3
CLK cycle time
CAS latency=2
CLK to valid
output delay
CAS latency=3
CAS latency=2
Output data
hold time
CAS latency=3
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
Symbol
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
-7
-8
-H
Min Max Min Max Min Max
7
8
10
1000
1000
1000
10
12
10
6
6
6
6
6
6
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
1
1
1
1
1
1
6
6
6
6
6
6
-L
-10
Unit
Min Max Min Max
10
10
1000
1000 ns
12
13
6
7
ns
7
8
3
3
ns
3
3
3
3.5
ns
3
3.5
ns
2
2.5
ns
1
1
ns
1
1
ns
6
7
ns
7
8
Note
1
1,2
2
3
3
3
3
2
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Output rise time
trh
Measure in linear
region : 1.2V ~1.8V
1.37
4.37
Output fall time
tfh
Measure in linear
region : 1.2V ~1.8V
1.30
3.8
Output rise time
trh
Measure in linear
region : 1.2V ~1.8V
2.8
3.9
5.6
Output fall time
tfh
Measure in linear
region : 1.2V ~1.8V
2.0
2.9
5.0
Notes : 1. Output rise and fall time must be guaranteed across VDD and process range.
2. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
3. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
4. Measured into 50pF only, use these values to characterize to.
5. All measurements done with respect to VSS.
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
4
4
1,2,3
1,2,3
-8-
Rev. 1.0 (Oct. 1999)