K4S160822D Datasheet, PDF (43/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

KM48S2120D
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
CMOS SDRAM
CLOCK
CKE
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSS
*Note 1
*Note 2
*Note 3
tSS
tSS
*Note 2
RAS
CAS
ADDR
Ra
Ca
BA
A10/AP
DQ
WE
Ra
tSHZ
Qa0 Qa1 Qa2
DQM
Precharge
Power-down
Entry
Row Active
Read
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
Precharge
: Don't care
*Note :
1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (32ms)
- 43
Rev.1.0 (Mar. 1999)