K4S160822D Datasheet, PDF (4/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

K4S160822D
PIN CONFIGURATION (Top view)
VDD 1
DQ0 2
VSSQ 3
DQ1 4
VDDQ 5
DQ2 6
VSSQ 7
DQ3 8
VDDQ 9
N.C 10
N.C 11
WE 12
CAS 13
RAS 14
CS 15
BA 16
A10/AP 17
A0 18
A1 19
A2 20
A3 21
VDD 22
CMOS SDRAM
44 VSS
43 DQ7
42 VSSQ
41 DQ6
40 VDDQ
39 DQ5
38 VSSQ
37 DQ4
36 VDDQ
35 N.C/RFU
34 N.C
33 DQM
32 CLK
31 CKE
30 N.C
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS
44Pin TSOP (II)
(400mil x 725mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System clock
CS
Chip select
CKE
Clock enable
A0 ~ A10/AP Address
BA
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM
Data input/output mask
DQ0 ~ 7
VDD/VSS
Data input/output
Power supply/ground
VDDQ/VSSQ Data output power/ground
N.C/RFU
No connection
/reserved for future use
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
-4-
Rev. 1.0 (Oct. 1999)