K4S160822D Datasheet, PDF (25/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

K4S160822D
12. About Burst Type Control
Basic
MODE
Sequential Counting
Interleave Counting
Random
MODE
Random column Access
tCCD = 1 CLK
13. About Burst Length Control
1
Basic
MODE
Special
MODE
Random
MODE
2
4
8
Full Page
BRSW
Burst Stop
Interrupt
MODE
RAS Interrupt
(Interrupted by Precharge)
CAS Interrupt
CMOS SDRAM
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page.
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = "010".
At MRS A2,1,0 = "011".
At MRS A2,1,0 = "111".
At the end of the burst length, burst will be stop automatically.
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, tRAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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Rev. 1.0 (Oct. 1999)