K4S160822D Datasheet, PDF (45/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

KM48S2120D
Mode Register Set Cycle
Auto Refresh Cycle
CMOS SDRAM
CLOCK
CKE
0 1 2 3 4 5 6 7 8 09 110 211 132 143 514 165 176 187 198 1109
HIGH
HIGH
CS
*Note 2
tRC
RAS
CAS
*Note 1
ADDR
*Note 3
Key
Ra
DQ
Hi-Z
Hi-Z
WE
DQM
MRS
New
Command
Auto Refresh
New Command
: Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
*Note :
MODE REGISTER SET CYCLE
1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
- 45
Rev.1.0 (Mar. 1999)