K4S160822D Datasheet, PDF (41/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

KM48S2120D
CMOS SDRAM
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
CLOCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
BA
A10/AP
RAa
DQ
WE
DQM
CAa
CAb
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
tRDL
*Note 2
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop Write
(A-Bank)
Precharge
(A-Bank)
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
: Don't care
- 41
Rev.1.0 (Mar. 1999)