K4S160822D Datasheet, PDF (42/46 Pages) Samsung semiconductor – 2Mx8 SDRAM 1M x 8bit x 2 Banks Synchronous DRAM LVTTL

KM48S2120D
Burst Read Single bit Write Cycle @Burst Length=2
CMOS SDRAM
CLOCK
CKE
012345
*Note 1
6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
CS
RAS
CAS
*Note 2
ADDR
RAa
CAa RBb CAb
RAc
CBc
CAd
BA
A10/AP
RAa
DQ CL=2
RBb
DAa0
RAc
QAb0 QAb1
DBc0
QAd0 QAd1
CL=3
DAa0
QAb0 QAb1
DBc0
QAd0 QAd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
- 42
Rev.1.0 (Mar. 1999)