M378T3354BG3-CD5 Datasheet, PDF (5/22 Pages) Samsung semiconductor – 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC

256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
CK0-CK2
CK0-CK2
CKE0-CKE1
S0-S1
RAS, CAS, WE
ODT0-ODT1
V_REF
V_DDQ
BA0-BA1
Type
Input
Input
Input
Input
Input
Supply
Supply
Input
Function
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge
of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
crossing)
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks,
CKE low initiates the Powe Down mode, or the Self-Refresh mode
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When
the command decoder is disbled, new command are ignored but previous operations continue. This signal provides
for external rank selection on systems with multiple ranks
RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
Reference voltage for SSTL 18 inputs.
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuf-
fered DIMM designs, VDDQ shares the same power plane as VDD pins.
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
A0-A13
DQ0-DQ63
CB0-CB7
DM0-DM8
V_DD,V_SS
DQS0-DQS8
DQS0-DQS8
SA0-SA2
SDA
SCL
V_DD SPD
Input
In/Out
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge
is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a pre-
charge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high,
all banks will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank
to precharge.
Data and Check Bit Input/Output pins.
Input
Supply
In/Out
Input
In/Out
Input
Supply
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input
data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading.
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V_DD/V_DDQ planes
on these modules.
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of
the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
These signals and tied at the system planar to either V_SS or V_DD to configure the serial SPD EERPOM address
range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus
time to VDD to act as a pullup onthe system board.
Power supply for SPD EEPROM. This supply is separate from the V_DD/V_DDQ power plane. EEPROM supply is oper-
able from 1.7V to 3.6V.
Rev. 1.5 Aug. 2005