M378T3354BG3-CD5 Datasheet, PDF (17/22 Pages) Samsung semiconductor – 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC

256MB, 512MB, 1GB Unbuffered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 °C < T_CASE < 95 °C; V_DDQ = 1.8V + 0.1V; V_DD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Refresh to active/Refresh command time
tRFC
Average periodic refresh interval
tREFI
Symbol
0 °C ≤ T_CASE ≤ 85°C
85 °C < T_CASE ≤ 95°C
256Mb
75
7.8
3.9
512Mb
105
7.8
3.9
1Gb
127.5
7.8
3.9
2Gb 4Gb Units
195 tbd
ns
7.8 7.8
µs
3.9 3.9
µs
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
tRP
tRC
tRAS
DDR2-533(D5)
4-4-4
min
max
5
8
3.75
8
-
-
15
15
55
40
70000
DDR2-400(CC)
3-3-3
min
max
5
8
5
8
-
-
15
15
55
40
70000
Units
ns
ns
ns
ns
ns
ns
ns
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH
tDS
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
DDR2-533
min
max
-500
+500
-450
+450
0.45
0.55
0.45
0.55
min(tCL, tCH)
x
3750
8000
225
x
100
x
0.6
x
0.35
x
x
tAC max
tAC min
tAC max
2* tACmin tAC max
x
300
x
400
tHP - tQHS
x
WL-0.25
WL+0.25
0.35
x
0.35
x
0.2
x
0.2
x
2
x
DDR2-400
min
max
-600
+600
-500
+500
0.45
0.55
0.45
0.55
min(tCL, tCH)
x
5000
8000
275
x
150
x
0.6
x
0.35
x
x
tAC max
tAC min
tAC max
2* tACmin
tAC max
x
350
x
450
tHP - tQHS
x
WL-0.25
WL+0.25
0.35
x
0.35
x
0.2
x
0.2
x
2
x
Units Notes
ps
ps
tCK
tCK
ps
20,21
ps
24
ps 15,16,17
ps 15,16,17
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
Rev. 1.5 Aug. 2005