KFG5616Q1A-DEB5 Datasheet, PDF (48/113 Pages) Samsung semiconductor – OneNAND Specification FLASH MEMORY

OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
Erase Interrupt (EI)
This is the Erase interrupt bit.
EI Interrupt [5]
Status
Conditions
sets itself to ’1’
clears to ’0’
At the completion of an Erase Operation
(0094h, 0095h, 0030h)
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
Reset Interrupt (RSTI)
This is the Reset interrupt bit.
RSTI Interrupt [4]
Status
Conditions
sets itself to ’1’
clears to ’0’
At the completion of an Reset Operation
(00B0h, 00F0h, 00F3h or
warm reset is released)
’0’ is written to this bit
Default State
Cold
Warm/hot
0
0
Default State
Cold
Warm/hot
0
1
Valid
State
0
0→1
1→0
Valid
State
0
0→1
1→0
Interrupt
Function
off
Pending
off
interrupt
Function
off
Pending
off
2.8.23 Start Block Address Register F24Ch (R/W)
This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock
Block' command, 'Unlock Block' command, or ’Lock-Tight' Command.
F24Ch, default = 0000h
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved(00000000)
SBA
Device
256Mb
Number of Block
512
SBA
[8:0]
SBA Information[9:0]
Item
SBA
Definition
Start Block Address
Description
Precedes Lock Block, Unlock Block, or Lock-Tight commands
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