KFG5616Q1A-DEB5 Datasheet, PDF (47/113 Pages) Samsung semiconductor – OneNAND Specification FLASH MEMORY

OneNAND256(KFG5616x1A-xxB5)
FLASH MEMORY
2.8.22 Interrupt Status Register F241h (R/W)
This Read/Write register shows status of the OneNAND interrupts.
F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INT
Reserved(0000000)
RI
WI
EI RSTI
Reserved(0000)
Interrupt (INT)
This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes
low if INTpol is high and goes high if INTpol is low.
INT Interrupt [15]
Status
Conditions
sets itself to ’1’
clears to ’0’
One or more of RI, WI, RSTI and EI is set to ’1’,
or 0065h, 0023h, 0071h, 002A and 002C com-
mands are completed
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
Default State
Cold
Warm/hot
1
1
Valid
State
0
0→1
1→0
interrupt
Function
off
Pending
off
Read Interrupt (RI)
This is the Read interrupt bit.
RI Interrupt [7]
Status
Conditions
sets itself to ’1’
clears to ’0’
At the completion of an Load Operation
(0000h, 0013h, Load Data into Buffer,
or boot is done)
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
Default State
Cold
Warm/hot
1
0
Write Interrupt (WI)
This is the Write interrupt bit.
WI Interrupt [6]
Status
Conditions
sets itself to ’1’
clears to ’0’
At the completion of an Program Operation
(0080h, 001Ah, 001Bh)
’0’ is written to this bit, or
Cold/Warm/Hot reset is being performed
Default State
Cold
Warm/hot
0
0
Valid
State
0
0→1
1→0
Valid
State
0
0→1
1→0
Interrupt
Function
off
Pending
off
interrupt
Function
off
Pending
off
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