K4D263238D Datasheet, PDF (4/18 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

K4D263238D
PIN CONFIGURATION (Top View)
128M DDR SDRAM
DQ29
81
VSSQ
82
DQ30
83
DQ31
84
VSS
85
VDDQ
86
N.C
87
N.C
88
N.C
89
N.C
90
N.C
91
VSSQ
92
RFU
93
DQS
94
VDDQ
95
VDD
96
DQ0
97
DQ1
98
VSSQ
99
DQ2
100
100 Pin TQFP
20 x 14 mm²
0.65mm pin Pitch
50
A7
49
A6
48
A5
47
A4
46
VSS
45
A9
44
N.C
43
N.C
42
N.C
41
N.C
40
N.C
39
N.C
38
N.C
37
A11
36
A10
35
VDD
34
A3
33
A2
32
A1
31
A0
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
DQS
DMi
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA0, BA1
A0 ~A11
DQ0 ~ DQ31
VDD
VSS
VDDQ
VSSQ
MCL
-4-
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ′s
Ground for DQ′s
Must Connect Low
Rev. 1.3 (Jul. 2002)