K4D263238D Datasheet, PDF (10/18 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

K4D263238D
128M DDR SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD
VDDQ
TSTG
PD
IOS
Value
Unit
-0.5 ~ 3.6
V
-1.0 ~ 3.6
V
-0.5 ~ 3.6
V
-55 ~ +150
°C
1.8
W
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)
Parameter
Device Supply voltage
Symbol
Min
Typ
Max
VDD
2.375
2.50
2.625
Output Supply voltage
VDDQ
2.375
2.50
2.625
Reference voltage
Termination voltage
Input logic high voltage
Input logic low voltage
VREF
Vtt
VIH
VIL
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.30
-
VREF
-
-
0.51*VDDQ
VREF+0.04
VDDQ+0.30
VREF-0.15
Output logic high voltage
VOH
Vtt+0.76
-
-
Output logic low voltage
VOL
-
-
Vtt-0.76
Input leakage current
IIL
-5
-
5
Output leakage current
IOL
-5
-
5
Unit
V
V
V
V
V
V
V
V
uA
uA
Note
1
1
2
3
4
5
IOH=-15.2mA
IOL=+15.2mA
6
6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to
peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error
and an additional + 25mV for AC noise.
3. Vtt of the transmitting device must track VREF of the receiving device.
4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate.
5. VIL(min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.
6. For any pin under test input of 0V ≤ VIN ≤ VDD is acceptable. For all other pins that are not under test VIN=0V.
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Rev. 1.3 (Jul. 2002)