K4D263238D Datasheet, PDF (12/18 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

K4D263238D
128M DDR SDRAM
AC OPERATING TEST CONDITIONS (VDD/ VDDQ=2.5V+ 5% , TA= 0 to 65°C)
Parameter
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Value
0.50*VDDQ
1.5
1.0
VREF+0.35/VREF-0.35
VREF
Vtt
See Fig.1
Unit
V
V
V/ns
V
V
V
Note
Vtt=0.5*VDDQ
Output
Z0=50Ω
CLOAD=30pF
RT=50Ω
VREF
=0.5*VDDQ
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz)
Parameter
Input capacitance( CK, CK )
Input capacitance(A0~A10, BA0~BA1)
Input capacitance
( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ0~DQ31)
Input capacitance(DM0 ~ DM3)
Symbol
CIN1
CIN2
CIN3
COUT
CIN4
Min
1.0
1.0
1.0
1.0
1.0
Max
5.0
4.0
4.0
6.0
6.0
Unit
pF
pF
pF
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
Symbol
CDC1
CDC2
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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Value
Unit
0.1 + 0.01
uF
0.1 + 0.01
uF
Rev. 1.3 (Jul. 2002)