K4D263238D Datasheet, PDF (13/18 Pages) Samsung semiconductor – 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

K4D263238D
AC CHARACTERISTICS
Parameter
CK cycle time
CL=3
CL=4
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
Clock half period
Data output hold time from DQS
Symbol
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
tHP
tQH
-40
Min
-
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-0.4
Max
8
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
-
-
128M DDR SDRAM
-50
Min
5.0
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.25
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-0.45
Max
10
0.55
0.55
+0.7
+0.7
+0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
-
-
Unit
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
Note
1
ns
1
ns
1
Simplified Timing @ BL=2, CL=3
0
1
CK, CK
CS
DQS
DQ
DM
COMMAND _READA
tCH
tCL
tCK
2
3
4
5
6
7
tRPRE
tDQSCK
tRPST
tDQSQ
tAC
Da1 Da2
tIS
tIH
tDQSS
tWPREH
tDQSH
tWPST
tWPRES
tDS tDH
Db0 Db1
8
Hi-Z
Hi-Z
- 13 -
WRITEB
Rev. 1.3 (Jul. 2002)