K4H560438D-GC Datasheet, PDF (23/26 Pages) Samsung semiconductor – DDR 256Mb

K4H561638D
AC Timming Parameters & Specifications
Parameter
Symbol
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
Output Slew Rate Matching Ratio(rise to fall)
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
tIH
tIS
tIH
tHZ
tLZ
tSL(I)
tSL(IO)
tSL(O)
tSLMR
B3
(DDR333)
Min
Max
60
72
42
70K
18
18
12
15
1
1
7.5
12
6
12
0.45
0.55
0.45
0.55
-0.6
+0.6
-0.7
+0.7
-
0.4
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.75
0.75
0.8
0.8
-0.7
+0.7
-0.7
+0.7
0.5
0.5
1.0
4.5
0.67
1.5
DDR SDRAM
A2
(DDR266A)
Min
Max
65
75
45
120K
20
20
15
15
1
1
7.5
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
-0.75
+0.75
-0.75
+0.75
0.5
0.5
1.0
4.5
0.67
1.5
B0
(DDR266B)
Min
Max
65
75
45
120K
20
20
15
15
1
1
10
12
7.5
12
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.5
0.9
1.1
0.4
0.6
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
1.1
0.9
0.9
1.0
1.0
-0.75
+0.75
-0.75
+0.75
0.5
0.5
1.0
4.5
0.67
1.5
Unit Note
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
5
ns
5
tCK
tCK
ns
ns
ns
5
tCK
tCK
tCK
ns
2
tCK
tCK
tCK
tCK
tCK
tCK
ns
6
ns
6
ns
6
ns
6
ns
ns
V/ns 6
V/ns 7
V/ns 10
Rev. 2.2 Mar. ’03
- 23 -