S6B0755 Datasheet, PDF (19/68 Pages) Samsung semiconductor – 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
PRELIMINARY SPEC. VER. 1.0
S6B0755
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 128-column addressable array. Each pixel
can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8
lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page
directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD
common lines as shown in Figure 7. The microprocessor can read from and write to RAM through the I/O buffer.
Since the LCD controller operates independently, data can be written into RAM at the same time as data is being
displayed without causing the LCD flicker.
DB0 0 0 1 - - 0
COM0
--
DB1 1 0 0 - - 1
COM1
--
DB2 0 1 1 - - 0
COM2
--
DB3 1 0 1 - - 0
COM3
--
DB4 0 0 0 - - 1
COM4
--
Display Data RAM
LCD Display
Figure 7. RAM-to-LCD Data Transfer
Page Address Circuit
This circuit is for providing a Page Address to Display Data RAM shown in Figure 9. It incorporates 4-bit Page
Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", DB2, DB1 and DB0 is
"L") is a special RAM area for the icons and display data DB0 is only valid.
Line Address Circuit
This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing
the contents of on-chip RAM as shown in Figure 9 & Figure 10. It incorporates 7-bit Line Address register
changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame,
the contents of register are copied to the line counter which is increased by CL signal and generates the Line
Address for transferring the 128-bit RAM data to the display data latch circuit. However, display data of icons are
not scrolled because the MPU can not access Line Address of icons.
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