S6B0755 Datasheet, PDF (12/68 Pages) Samsung semiconductor – 128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD

S6B0755
PRELIMINARY SPEC. VER. 1.0
128 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
MICROPROCESSOR INTERFACE
Name
RESETB
PS0
PS1
CS1B
RS
RW_WR
Table 4. Microprocessor Interface Pins
I/O
Description
Reset the input pin
I
When RESETB is "L", initialization is executed.
Parallel/Serial data input select input
PS0 Interface
Data/
Mode
Instruction
Data
Read / Write Serial Clock
I
H
Parallel
RS
DB0 to DB7
E_RD
RW_WR
-
L
Serial
RS or None SID(DB7)
Write only
SCLK(DB6)
*NOTE: When PS is "L", DB0 to DB5 are high impedance and E_RD and RW_WR
must be fixed to either "H" or "L".
Microprocessor interface select input pin
− PS0 = “H” , PS1 = "H": 6800-series parallel MPU interface
I
− PS0 = “H” , PS1 = "L": 8080-series parallel MPU interface
− PS0 = “L” , PS1 = "H": 4 Pin-SPI serial MPU interface
− PS0 = “L” , PS1 = "L": 3 Pin-SPI serial MPU interface
Chip select input pins
I
Data/instruction I/O is enabled only when CS1B is "L" . When chip select is non-active,
DB0 to DB7 may be high impedance.
Register select input pin
I
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
PS1 MPU Type RW_WR
Description
Read/Write control input pin
H 6800-series
RW
− RW = "H": read
I
− RW = "L": write
L 8080-series
Write enable clock input pin
/WR
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
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