S6A0092 Datasheet, PDF (16/54 Pages) Samsung semiconductor – 80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
IF
MI
CSB
RS
RW_WR
E_RD
DB7_∼DB4
upper
4-bit
lower
4-bit
Instruction Write
NOP
Dummy Read
lower
4-bit
upper
4-bit
RAM Read
upper
4-bit
lower
4-bit
Data Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
Interface with MPU in Serial Mode (PS = "Low")
When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, RESETB
(reset input), SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and
CSB (chip selection input) are used.
By setting CSB to "Low", S6A0092 can receive SCL input. If CSB is set to "High", S6A0092 resets the internal 8-bit
shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial
data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6).
At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS input
of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).
CSB
S I (D B 7 )
SCL (DB6)
RS
D7 D6 D5 D4 D3 D2 D1 D0 D7
1
2
3
4
5
6
7
8
9
Figure 7. Timing Diagram of Serial Data Transfer
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