S6A0092 Datasheet, PDF (14/54 Pages) Samsung semiconductor – 80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

S6A0092
26 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Mode (PS = "High")
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and one
of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to store
instruction code transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used as
temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAMs is selected
by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit bus mode
(figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting, first and
second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy read make the
address counter (AC) increased by 1. So it is recommended to set address again before writing. The instruction read
cycle is not supported and it is regarded as a no operation cycle.
In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7∼DB4) by two times. The high order bits (for 8-bit
mode DB7∼DB4) are written before the low order bits (for 8-bit mode DB3∼DB0) in write and low order bits (for 8-bit
mode DB3∼DB0) are read before the high order bits (for 8-bit mode DB7∼DB4) in read transaction. The DB0∼DB3
pins are floated in this 4-bit bus mode. After RESETB resets, S6A0092 considers first 4-bit data from MPU as the
high order bits.
IF
MI
CSB
RS
RW_WR
E_RD
DB7_∼DB0
Instruction
Write
NOP
Valid
Data
Dummy
Read
RAM
Read
Data
Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
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