S6A0092 Datasheet, PDF (11/54 Pages) Samsung semiconductor – 80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD

80 COM / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0092
Name
System control
CK
MI
PS
IF
DIRS
MPU interface
RESETB
CSB
RS
RW_WR
E_RD
Table 3. Pin Description (Continued)
I/O
Description
External clock input. It must be fixed to "High" or "Low" when the internal
I
oscillation circuit is used. In case of the external clock mode, CK is used as the
clock and OS bit should be OFF.
MPU interface selection input
I
MI = "Low": 80-series MPU
MI = "High": 68-series MPU
Parallel / serial selection input
I
When PS = "Low": serial mode
When PS = "High": 4-bit/8-bit bus mode
Interface data length selection pin for parallel data input
When PS = "Low"
I
IF = "Low" or "High": serial interface mode
When PS = High
IF = "Low": 4-bit bus mode
IF = "High": 8-bit bus mode
SEG direction selection input
When DIRS = "Low”
I
SEG1 → SEG2 → SEG79 → SEG80
When DIRS = "High”
SEG80 → SEG79 → SEG2 → SEG1
I
Reset input
S6A0092 is initialized while RESETB is low.
I
Chip selection input
S6A0092 is selected while CSB is low.
Register selection input
I
When RS = "Low", instruction register
When RS = "High", data register.
In 80-series MPU interface mode
This pin is connected to WR pin of MPU and is a active low write signal
I
In 68-series MPU interface mode
This pin is connected to R/W pin of MPU
When RW_WR = "Low", write mode
When RW_WR = "High", read mode
In 80-series MPU interface mode
This pin is connected to RD pin of MPU and is a active low read signal
I
In 68-series MPU interface mode
This pin is connected to E pin of MPU and enable read or write command
according to RW_WR signal.
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