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K4R271669F Datasheet, PDF (14/20 Pages) Samsung semiconductor – 128Mbit RDRAM(F-die)
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K4R271669F
Direct RDRAM™
Timing Conditions
Table 11: Timing Conditions
Symbol
tCYCLE
tCR, tCF
tCH, tCL
tTR
tDCW
tDR, tDF
tS, tH
tDR1, tDF1
tDR2, tDF2
tCYCLE1
tCH1, tCL1
tS1
tH1
tS2
tH2
tS3
tH3
tS4
tH4
tNPQ
tREADTOCC
tCCSAMTOREAD
tCE
tCD
tFRM
tNLIMIT
tREF
tBURST
tCCTRL
Parameter
Min
CTM and CFM cycle times (-800)
2.50
CTM and CFM input rise and fall times. Use the minimum value of
these parameters during testing.
0.2
CTM and CFM high and low times
40%
CTM-CFM differential (MSE/MS=0/0)
0.0
CTM-CFM differential (MSE/MS=1/1) a
0.9
Domain crossing window
-0.1
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the min-
imum value of these parameters during testing.
DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=2.50ns
SIO0, SIO1 input rise and fall times
0.2
0.250b
-
CMD, SCK input rise and fall times
-
SCK cycle time - Serial control register transactions
1000
SCK cycle time - Power transitions
10
SCK high and low times
4.25
CMD setup time to SCK rising or falling edgec
1.25
CMD hold time to SCK rising or falling edgec
1
SIO0 setup time to SCK falling edge
40
SIO0 hold time to SCK falling edge
40
PDEV setup time on DQA5..0 to SCK rising edge.
0
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
ROW2..0, COL4..0 setup time for quiet window
-1
ROW2..0, COL4..0 hold time for quiet windowd
5
Quiet on ROW/COL bits during NAP/PDN entry
4
Offset between read data and CC packets (same device)
12
Offset between CC packet and read data (same device)
8
CTM/CFM stable before NAP/PDN exit
2
CTM/CFM stable after NAP/PDN entry
100
ROW packet to COL packet ATTN framing delay
7
Maximum time in NAP mode
Refresh interval
Interval after PDN or NAP (with self-refresh) exit in which all banks of
the RDRAM device must be refreshed at least once.
Current control interval
34 tCYCLE
Max
3.83
0.5
60%
1.0
1.0
0.1
0.65
-
5.0
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10.0
32
200
100ms
Unit
ns
Figure(s)
Figure 56
ns
Figure 56
tCYCLE
tCYCLE
tCYCLE
ns
Figure 56
Figure 43
Figure 56
Figure 62
Figure 57
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
tCYCLE
µs
ms
Figure 57
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 59
Figure 50
Figure 60
Figure 50
Figure 50
Figure 49
Figure 54
Figure 54
Figure 50
Figure 49
Figure 48
Figure 47
Figure 52
µs
Figure 53
ms/tCYCLE Figure 54
Page 12
Version 1.41 Jan. 2004
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