H8S2138 Datasheet, PDF (974/1061 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Appendix B Internal I/O Registers
SARX1—Second Slave Address Register 1
SAR1—Slave Address Register 1
SARX0—Second Slave Address Register 0
SAR0—Slave Address Register 0
H'FF8E
H'FF8F
H'FFDE
H'FFDF
SAR
Bit
Initial value
Read/Write
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
IIC1
IIC1
IIC0
IIC0
0
FS
0
R/W
SARX
Slave address
Format select
Bit
7
6
5
4
3
2
1
0
SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
Initial value
0
0
0
0
0
0
0
1
Read/Write R/W
R/W R/W
R/W R/W R/W
R/W R/W
Format select
DDCSWR
Bit 6
SAR
Bit 0
SW
FS
0
0
1
1
0
1
Second slave address
SARX
Bit 0
FSX
0
1
0
1
0
1
0
1
Operating Mode
I²C bus format
• SAR and SARX slave addresses recognized
I²C bus format
• SAR slave address recognized
• SARX slave address ignored
I²C bus format
• SAR slave address ignored
• SARX slave address recognized
Synchronous serial format
• SAR and SARX slave addresses ignored
Formatless mode (start/stop conditions not
detected)
• Acknowledge bit used
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not set this mode when automatic switching to the I²C bus format is
performed by means of the DDCSWR setting.
Rev. 4.00 Jun 06, 2006 page 920 of 1004
REJ09B0301-0400