H8S2138 Datasheet, PDF (340/1061 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 11 16-Bit Free-Running Timer
Bit 1
OLVLA
0
1
Description
0 output at compare-match A
1 output at compare-match A
(Initial value)
Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in
response to compare-match B (signal indicating a match between the FRC and OCRB values).
Bit 0
OLVLB
0
1
Description
0 output at compare-match B
1 output at compare-match B
(Initial value)
11.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and
module stop mode is entered. For details, see section 24.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode.
MSTPCRH
Bit 5
MSTP13
0
1
Description
FRT module stop mode is cleared
FRT module stop mode is set
(Initial value)
Rev. 4.00 Jun 06, 2006 page 286 of 1004
REJ09B0301-0400