H8S2138 Datasheet, PDF (746/1061 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 24 Power-Down State
φ,
supporting module
clock
Bus master clock
Medium-speed mode
Internal address
bus
SBYCR
SBYCR
Internal write signal
Figure 24.2 Medium-Speed Mode Transition and Clearance Timing
24.4 Sleep Mode
24.4.1 Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR
are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the
contents of the CPU’s internal registers are retained. Other supporting modules do not stop.
24.4.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and
interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or
if interrupts other than NMI have been masked by the CPU.
Clearing with the RES Pin: When the RES pin is driven low, the reset state is entered. When the
RES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware
standby mode.
Rev. 4.00 Jun 06, 2006 page 692 of 1004
REJ09B0301-0400