H8S2138 Datasheet, PDF (518/1061 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Section 16 I²C Bus Interface [H8S/2138 Group Option]
DDCSWR SAR
Bit 6
Bit 0
SARX
Bit 0
SW
FS
FSX
Operating Mode
0
0
0
I²C bus format
• SAR and SARX slave addresses recognized
1
I²C bus format
(Initial value)
• SAR slave address recognized
1
0
• SARX slave address ignored
I²C bus format
• SAR slave address ignored
• SARX slave address recognized
1
Synchronous serial format
• SAR and SARX slave addresses ignored
1
0
0
Formatless mode (start/stop conditions not detected)
0
1
1
0
1
1
• Acknowledge bit used
Formatless mode^* (start/stop conditions not detected)
• No acknowledge bit
Note: * Do not set this mode when automatic switching to the I²C bus format is performed by
means of the DDCSWR setting.
16.2.3 Second Slave Address Register (SARX)
Bit
Initial value
Read/Write
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
0
FSX
1
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Rev. 4.00 Jun 06, 2006 page 464 of 1004
REJ09B0301-0400